Essays --

The CMOS technology plays a major role on the writ of execution of microprocessors on very large scale integ postd roach chips. The rapid growth in CMOS technology with theshrinking transistor coat towards 16nm has allowed forplacement of several billions of transistors on a mavinmicroprocessor chip. This also leads to lessen the delay of logicgates in the order of pico seconds. One such(prenominal) method to improvethe exertion of microprocessor is to optimize the measureperformance of ever-changing rophys. In this paper a full addercircuit is knowing and simulated employ rate sensing keepertechnique with L=0.12m technology and VDD=1.2 V forimproving the timing and noise valuation reserve also the noise tolerancecharacteristics of the full adder circuit designed using ratesensing keeper is compared with twin transistor establish full addercircuit.Keywords Bias,Domino logic, noise tolerance, rate sensing,timing optimization.I. INTRODUCTIONHE rapid advancement in semiconduc tor technology withthe shrinking transistor size towards 16nm has allowed forplacement of several billion transistors on a singlemicroprocessor chip1. CMOS technology plays a major roleon the performance of VLSI microprocessors 2.The timingperformance of the microprocessor can be improved by using high-power circuits in microprocessors 3. However the usage ofdynamic circuits in microprocessors is limited repayable to manychallenges including transistor sizing, charge sharing, leakage up-to-the-minute, noise immunity and environmental and semiconductorprocess variations etc 4.Timing optimization of dynamiccircuits can be achieved by means of several methods such astransistor sizing, using multiple wand voltagesetc.5,6,7.The aggressive scaling of transistors andinterc... ... andthe experimental results shows that the full adder circuitdesigned using rate sensing keeper transistor technique gives pukka performance compared to the other alternatives suchas Conditional Keeper (CKP) a nd current mirror-based keeper(LCR).Fig.22. Output noise Vs Vbias characteristics of full adder using station SensingKeeper techniqueIV. CONCLUSIONIn this paper the performance of a full adder circuitdesigned using rate sensing keeper transistor technique isanalyzed in power point and its performance is compared with otherfull adder circuits. The full adder circuit is simulated usingL=0.12m technology along with tot up voltage VDD=1.2V.The experimental results shows that the full adder circuitdesigned using rate sensing keeper transistor technique givessuperior performance compared to full adder circuits designedusing conventional domino techniques.